I received a question last week from a reader about what page tables are and how are they used in Windows CE6.  Since this is where a large portion of the changes for CE6 have been implemented, it might be a good idea to make sure that everyone is on the same "page" about them.  (No pun intended, well I guess it was. :))

What is an Memory Management Unit (MMU) and Virtual Memory?

In the early 80's (and in some cases today), microprocessors usually accessed physical memory by mapping all physical memory addresses directly to the external bus.  This would mean that the microprocessor's physical memory addresses were mapped one to one to the external memory locations on a system.  This would create a situation in which the software running on the microprocessor could access all of the physical memory on the system at any time.  This would rely heavily on the programmer to ensure that they did not overwrite code or data that they were not intending to.  There was no form of protection between different pieces of code and the system memory. 

Therefore, the memory management unit was created to solve multiple problems:

• Memory Protection through the use of Virtual Memory

By adding a layer of abstraction between the microprocessor's "virtual" memory locations and their actual physical locations, the software programmer can now define areas of the physical memory map that are accessible only after it has been preallocated in the virtual memory map.  This means that if the code "accidentally" reads or writes from memory that is not preallocated, the developer will be warned of a problem in the execution of this code and can take action. 
It also allows the programmer to protect physical memory from certain pieces of code by changing the mapping between virtual and physical memory dynamically.  This is how most modern operating systems implement a large portion of their security model.  

• Finer Cache Control

By having a MMU, the programmer can define certain regions of virtual memory that are mapped to either cached or uncached physical memory.  The MMU allows this to occur even at a page level.

• Physical memory fragmentation

Since the MMU creates an abstraction layer between the virtual and physical addresses, it is possible to create a contiguous region of memory even when the underlying physical memory is fragmented.  This can give an operating system programmer the flexibility to create a virtual memory map that is completely independent of the underlying physical memory structure and usage.
What are page tables?

The mapping of virtual memory to physical memory is accomplished through the use of what is called "page tables".  Let's take the ARMv4 processor architecture in Windows CE6 as a specific example to help explain this.  This architecture relies on two page table levels to map sections of physical memory to any virtual memory address from 0 to 4GB.  These page tables are accessed by the microprocessor's hardware directly in physical memory to make this translation as inexpensive and non obtrusive as possible. 

First Level Page Table Descriptors

The first level page table contains a number of descriptors that define a window of memory that represents 1 megabyte of virtual memory.  These 1 megabyte windows are called sections.  Each of these descriptors take 32bits of physical memory storage space.  In some cases, the first level page table is all that is needed to map physical memory to virtual memory.  The OEMAddressTable is a good example of this.  In other cases the second level page table descriptors are used.

Second Level Page Table Descriptors

Each first level page table descriptor can point to one or more second level page table descriptors which define a page of virtual memory and point to a page of physical memory.  These page table descriptors can point to 1KB, 4KB or 64KB regions, but CE6 has chosen to use either 4KB or 64KB of memory for each of these descriptors depending on the type and size of the allocation.  Each of these descriptors also take 32 bits of physical memory storage space.

Cacheable and Bufferable

Each page table descriptor defines whether or not a given virtual memory page is cached and/or buffered by the microprocessor when it accesses the physical memory.  You may hear from time to time about the C and B bits.  This refers to the cacheable and bufferable bits respectively.

Access Permissions

In addition to defining the translation between virtual and physical memory, the page table descriptors define access permissions to the physical memory that they describe.  This includes protection from writing, reading and code that is executed in user versus supervisor mode.

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Jason Browne
Director Platform Software Engineer
Professional Engineering Services
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